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**Introduction**

Switched-mode power supply (SMPS) has the advantage of high efficiency compared to traditional Low-dropout (LDO) regulators. Due to its switching nature, a SMPS emits noise at its switching frequency and its harmonics. This article illustrates the procedure of designing filtering to achieve ultra-low output voltage noise of SMPS regulators. Single stage capacitive filter is commonly used for DC-DC converter applications. Low-ESR ceramic capacitors are utilized to meet output voltage ripple specifications. The single stage capacitive filter is sufficient for applications that requires no less than 1-2mV output voltage ripple. For applications such as RF ADC and DAC applications where it is necessary to meet less than 1mV ripple, a second stage LC filter should be used to effectively suppress the switching noise.

** Single stage filter design**

A synchronous buck converter consists of an input capacitor CIN, two switches S1 and S2 with their body diodes, an energy storage power inductor L, and output capacitors, COUT. The input source provides energy to the power inductor L and the load when S1 is turned on and S2 is turned off. During this period, the inductor current rises. The energy stored in the inductor is transferred to the output capacitor and load when S2 is on and S1 is off, causing the inductor current to drop. The switching behavior of the buck regulator causes the output voltage to fluctuate. The output capacitors C_{OUT} is placed at the output to smooth the output voltage under steady state. The output capacitor reduces the output voltage ripple by providing a low impedance path for the high-frequency voltage components to return to ground.

In the subsequent development, it is assumed the buck converter operates under continuous conduction mode (CCM) for output voltage ripple minimization. The inductance of L is designed to meet inductor current ripple requirement. The minimum inductance of L is determined as:

L_{Min}=((V_{IN} – V_{OUT})^{D})/(I_{L,p-p} f_{SW}) (1)

Where VIN and VOUT represent the input and output voltage, respectively, D=V_{OUT}/V_{IN} represents the duty ratio, IL,p-p is the peak-to-peak current ripple of the inductor, and fSW represents the switching frequency of the converter. Typically, the peak-to-peak inductor current ripple is selected as 20-40% of the output DC current.

The output capacitance is selected to ensure that the output ripple is below the specified peak-to-peak value. For a single stage capacitive filter, an minimum output voltage ripple of 1mV to 2mV can be achieved.

Under steady state, the net electric charge delivered to the capacitor is zero within one switching period. The capacitor charge of the shaded area in Figure 1 is calculated as:

∆Q_{C} = T/4*I_{L,p-p}/2 (2)

Where T is the period of one switching cycle. By definition, the capacitor charge in a given period is also can also be expressed as:

∆Q_{C} = C∆V_{C} (3)

Equating equations (2) and (3), the minimum capacitance to achieve the required output peak-to-peak voltage ripple, V_{OUT,p-p} is determined as:

C_{Min} = I_{L,p-p}/(8f_{SW} ∆V_{C,p-p}) (4)

Ideally, the noise shunt capability can be increased by paralleling more output capacitors. In practical, the output capacitors are laterally placed on a PCB. Adding more output capacitors on a PCB would introduce additional parasitic inductance and AC resistance to the shunt path and thus reduce the effectiveness of bypassing the switching noise.

A typical PCB layout of a MPS power module which integrates optimized inductors to simplify the power converter design is shown in Figure 2. In the PCB layout of MPM3833C, wide copper plane is used for the output power path to minimize power losses. The output capacitors are placed along the output current path. As shown in the figure, as more capacitors are placed on the output plane, the distance from the additional capacitor to the output pin of the power module increases. Consequently, more parasitic inductance is involved in the output capacitor that is further away from the power module. Adding more output capacitance become less and less effective and eventually, the shunt loop is dominant by parasitic inductance.

To demonstrate the impact of loop parasitic inductance, an MPM3833C with various output capacitors are simulated using Simplis. It is assumed that each additional output capacitor introduces an additional 0.5nH parasitic inductance to the bypassing loop. Figure 3 illustrate the output ripple of the power module with one 22uF capacitor. The bypassing capacitor effectively reduces the output ripple to around 3mV at 5V input, 1.2V output, and 2A load.

To further reduce the output voltage ripple, 1 additional 22uF output capacitors is place at the output. Since the new capacitor has to be placed further away from the power module, the parasitic inductance involved with the new capacitors is 1nH. The simulated output voltage ripple is shown in Figure 4(a) where the output voltage ripple is reduced to 2mV. Compared to the waveform shown in Figure 3, where one 22uF output capacitor effectively brings down the output voltage ripple to 3mV, the additional one 22uF capacitor is less effective. Figure 4(b) shows the output voltage ripple with one more 22uF capacitor (total of 4×22uF). The last 22uF capacitor involves 1.5nH parasitic inductance in its bypassing loop. As shown in the figure, the output ripple reduction achieved by the additional 22uF capacitor is less than 5% compared to the case where 3×22uF is used.

As demonstrated in Figures 3 and 4, the parasitic inductance introduced by the PCB copper/trace will become dominant as more output capacitors are placed on the PCB. Eventually, the benefit of adding more capacitors will be negated by the additional parasitic inductance added in the loop.

**Second stage filter design**

Typically, the shunt output capacitor can effectively reduce the output voltage ripple to 1mV. Beyond this point, a second stage output filter is required to achieve smaller output voltage ripple (sub 1mV voltage ripple can be achieved). Figure 5 illustrates a second stage LC filter which is cascaded to the first stage output capacitors. The second stage filter consist of one filter inductor and its series resistor DCR, a bypassing capacitor branch, and a damping branch. The LC filter works by creating a high impedance to the output.

The filtering inductor L_{f} is resistive at the intended high frequency range and dissipates the noise energy in the form of heat. The inductor combines with additional shunt capacitors to form a low-pass LC filter network.

The second stage filter is very effective on reducing the output voltage noise when properly designed. It is crucial to size the component of the second stage LC filter for the intended frequency band. The first step of the design procedure involves choosing the first stage output capacitor such based on Equation (4). 5mV to 10mV output voltage ripple is typical for the first stage design. Usually a 10-22uF capacitor is sufficient. The capacitor C_{OUT} of the first stage has to be smaller than the bypassing capacitor C1 of the second stage to ensure system stability.

Once the first stage capacitor C_{OUT} is determined and the specified output voltage ripple (at given frequency) is given, the required attenuation of the second stage LC filter can be determined as:

A_{0,dB} = 20log V_{O,p-p}/V_{1,p-p} (5)

Where V_{1,p-p} represents peak to peak voltage ripple at the output capacitor and Vo,p-p represents the peak to peak of the output voltage (after the second stage filter).

Using phasor analysis, the amplitude of the gain of the LC filter is determined as

|H(f)|=1/√([1-(2πf)^{2}*L_{f}*C_{1}]^{2}+(ωR_{DC}*C_{1})^{2} (6)

Note that the impedance of the damping branch which consists a large series resistor is much larger than the bypassing branch at switching frequency. Thus the filter shown in Figure 5 is approximated as a second order RLC filter.

The cut-off frequency of the filter is determined as

f_{0} = 1/(2π√(L_{f}*C_{1})) (7)

Typically, an inductor with 0.22uH to 1uH inductance can be selected to achieve the required output ripple. The inductor should be selected to have minimal DCR as the serious resistance increases power dissipation and reduces the output voltage regulation. It should be noted that as the DC current increases, the core material of the inductor becomes saturated which reduces the inductance of the inductor. Care should be taken to ensure that the inductance is high enough at the rated DC current.

Once the filtering inductor is selected, its DCR can be extracted from the datasheet. The second stage LC filter which is a second order filter provides 40db per decade roll-off after the cutoff frequency. The attenuation at given frequency can be estimated as:

A(f) = -40log(f/f_{0})dB (8)

Using the attenuation calculated in equation (5), the required cut-off frequency is determined as:

f_{0} = f/10^{(A0/(-40))} (9)

Subsequently, the required bypassing capacitance C1 is determined as:

C_{1} = 1/(4π^{2}*f_{0}^{2}*L_{f}) (10)

Ceramic capacitors should be used as the bypassing capacitor for the low ESR and ESL. It should be noted that the capacitance of ceramic capacitors experience significant de-rating at DC bias voltage. Figure 6 illustrates the DC de-rating curve of a Murata 0805 ceramic capacitor which is rated at 6.3V. As shown in the figure, at the full rated DC bias voltage, the capacitance drops to 20% of the nominal value. The bypassing capacitor should be selected at the nominal DC bias voltage to factor in the de-rating.

**Damping**

The second stage LC filter may introduce resonance peaking if not properly damped. The resonance between the filtering inductor and bypassing capacitor may amplify the output ripple and create undesired ringing at load transient. Figure 7 shows the output voltage of an underdamped converter system with the second stage LC filter. Initially, the system operates under steady state. At t=200uS, a load transient from 1A to 2A is initiated which causes the output voltage to ring.

Figure 7(b) illustrate the output voltage and current under load transient of a overdamped second stage filter. To avoid undesired ringing at load transient, the second stage LC filter resonance must be properly damped. In most designs, the second stage filter will be placed outside of the control loop to avoid control stability issue. Consequently, the damping has to be achieved by passive components (additional damping resistors).

The filtering inductor usually include a parasitic DC resistance in series with the inductor. This DCR provides damping to the network. However, to provide enough damping for a series RLC circuit, the series resistance has to satisfy R_{DC} > 2√(L_{f}/C_{1}). In most cases, the DCR alone cannot provide sufficient damping. To this end, a RC damping network is inserted in parallel with the bypassing capacitors to damp the resonant circuit along with the series DCR resistor.

**Design example**

The EVREF0102A is the analog power module developed for ZCU1275 Zynq UltraScale+RFSoC Characterization Kit. The EVREF0102 analog power module provides ultra-low noise power supply for the high speed data converters on the ZCU1275 development kit.

The EVREF0102A employs five high efficiency step-down switched-mode power modules with integrated inductors. MPM3833C is a 6V, 3A, ultra-small step down power module and MPM 3683-7 is a 16V, 8A power module. Both power modules feature integrated protection functions including OCP, OVP, UVP, and OTP. Compared to the traditional LDO solution, EVREF0102A can achieve up to 80% efficiency improvement. The EVREF0102A analog power module also achieves ultra-low noise level to meet the specifications of Xilinx high-speed data converter by leveraging the forced continuous conduction mode (CCM) operation and implementing post passive filters.

CLC passive filters are utilized for the two most sensitive ADC and DAC rails and capacitive filters are utilized for the rest of power rails. The design procedure is illustrated on the ADC_AVCC rail where MPM3833C power module is employed to power the rail.

The MPM3833C integrates a 1uH power inductor, the current ripple of the inductor at 5V input and 0.925V output is determined as 0.63A by applying equation (1). Subsequently, the first stage output capacitor is selected based on equation (4) as 22uF to provide 3mV voltage ripple to the second stage filter.

The required gain of the second stage LC filter is determined by equation (5) as -30 dB to achieve 120uV output voltage ripple at the switching frequency. Considering the size and current rating availability, a 0.24uH Murata chip inductor DFE201612E-R24 is selected with sufficient current rating. The ADC and DAC rails require ultra-low noise across the frequency range up to 15MHz. To provide attenuation with enough margin, the cut-off frequency of the second stage filter is selected as 25kHz. Finally, the filtering capacitors are selected as 150uF. This design is conservative to provide enough margin. The cut-off frequency is selected to compensate the high-frequency gain increase due to the parasitic inductive impedance involved in the filter loop increases at high-frequency (up to 15MHz). A SP-Cap with 100mOhm ESR is selected as the damping capacitor. Since the series resistor of the SP-Cap is high enough for damping, there is no need to external resistor.

The FFT results of the output noise measurement of the EVREF0102A is shown in Figure 9. As shown in the figure, the peak noise at switching frequency is reduced to 14 uV.

**Conclusion**

The design procedure of an output filter is outlined in this article for a buck regulator to achieve ultra-low output voltage noise. A single stage output capacitor filter is capable of reducing the output voltage ripple to up to 2mV. A second stage LC filter is added to effectively reduce the output voltage ripple to less than 1mV. The design of the second LC filter involves selecting of the filtering inductor, the bypassing capacitor, and the damping branch. A design example is given for the power rail of high-speed ADC converter on Xilinx ZCU 1275 kit. The optimized filter effectively removes the output voltage ripple to satisfy the ultra-low noise requirement of on the ADC/DAC rails.

For further information:

**Gergely Balogh**, Field Sales Engineer

Phone: +36 30 867 0687

e-mail: gergely.balogh@codico.com

**CODICO**

https://www.codico.com