Altera Introduces SoC FPGAs: Integrating ARM Processor System and FPGA into 28-nm Single-Chip Solution

by donpedro

Altera Corporation unveiled its family of ARM-based SoC FPGAs, integrating 28-nm Cyclone® V and Arria® V FPGA fabric, a dual-core ARM® Cortex™-A9 MPCore™ processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip. These SoC FPGAs inherit ARM’s rich ecosystem of software development tools, debuggers, operating systems, middleware and applications. Users can leverage Altera’s SoC FPGA development flow to quickly create customized ARM-based systems that reduce embedded system board size, power and cost, while boosting performance in a variety of industries, including automotive, industrial, video surveillance, wireless infrastructure, computer and storage.

“SoC FPGAs based on 28nm process technology represent an exciting new development for embedded systems in terms of performance and increased capacity,” said Jim Nicholas, vice president marketing, processor division, ARM. “These devices offer great promise by enabling embedded system designers to reduce time to market, decrease costs and improve energy efficiency, while benefiting from the broad support of the ARM software ecosystem.”

Altera’s Cyclone V and Arria V SoC FPGAs feature a processor system with a dual-core 800 MHz ARM Cortex-A9 MPCore processor, NEON media processing engine, single/double-precision floating point unit, L1 and L2 caches, ECC-protected memory controllers, ECC-protected scratchpad memory and a wide range of commonly used peripherals. The processor system can deliver 4,000 DMIPS peak performance for less than 1.8 watts. The processor system and FPGA fabric are powered independently and can be configured and booted in any order. Once in operation, the FPGA portion can be powered down as needed to conserve system power.
The ARM Cortex-A9 MPCore processor system and FPGA are interconnected by high throughput data paths, providing over 125-Gbps peak bandwidth with integrated data coherency. This level of performance is not possible in two-chip solutions. An integrated single-chip SoC FPGA allows board designers to eliminate the external I/O paths between a processor and an FPGA, providing significant system power savings.

Altera’s Family of SoC FPGAs
Altera’s family of SoC FPGAs leverage its 28-nm product portfolio, which are tailored to meet customers’ power, performance and cost requirements by innovating in several areas, including process technology, transceiver technology, I/O resources and hard IP. The introduction of Cyclone V and Arria V SoC FPGAs extend the portfolio’s reach into the embedded processing market.
The Cyclone V and Arria V SoC FPGAs are based on a low-power 28-nm process (28LP). These families feature embedded transceivers that operate up to 5-Gbps and 10-Gbps respectively. The FPGA fabric includes variable-precision DSP blocks and up to three ECC-protected memory controllers. Altera’s Cyclone V SoC FPGAs feature up to 110K logic elements (LEs) and provide the industry’s lowest system cost and power, along with performance levels that make the devices ideal for differentiating high-volume applications, including next-generation industrial drive on a chip, advanced driver assistance and video surveillance. Arria V SoC FPGAs balance cost and performance while delivering the lowest total power for mid-range applications. The devices feature up to 460K LEs and are ideal for meeting the higher performance requirements in applications that include remote radio heads, LTE base stations and multi-function printers.

SoC FPGA Development Environment
Altera’s SoC FPGAs enable both hardware and software teams to maximize their productivity by using common tools and development flows that support both the Cortex-A9 MPCore processor and the FPGA. Designers can create custom peripherals and hardware accelerators using Altera’s Quartus® II software and integrate them with the processor system using Altera’s Qsys system integration tool. Qsys accelerates the hardware design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys automatically generates an FPGA-optimized network-on-a-chip (NoC) interconnect, delivering higher performance, enabling improved design reuse and providing faster verification. Qsys supports industry-standard interfaces including Avalon® Memory-Mapped, Avalon Streaming and AMBA® AXITM from ARM, enabling users to leverage and reuse IP cores with multiple interfaces in a single design. Because SoC FPGAs are based on the standard ARM Cortex-A9 MPCore processor, they are compatible with the existing ARM software ecosystem. Software development for systems based on SoC FPGAs can begin immediately on Altera’s SoC FPGA Virtual Target.

“With the integration of a high-performance processing system, low-power 28-nm FPGA fabric, a hardware-software development flow and Virtual Target development platform, Altera is setting a new standard in SoC technology,” said Vince Hu, vice president of product and corporate marketing, Altera Corporation. “As a part of Altera’s overall embedded initiative, SoC FPGAs deliver a dramatic improvement in system performance, power, cost and board size for embedded developers.”


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