Altera and ARM Expand Strategic Partnership for SoC Development Tools

by donpedro

Altera Corporation and ARM announced a long-term agreement to expand their strategic partnership for best-in-class embedded software development tools for SoC FPGAs. In

2012, Altera and ARM announced the creation of the ARM® Development Studio 5 (DS-5™) Altera® Edition, which pioneered the invention of FPGA-Adaptive Debugging for SoC FPGAs. Through the expanded agreement announced today, the ARM DS-5 Altera Edition toolkit is being enlarged to include the following additional tools:

• ARM Compiler 5 and ARM Compiler 6, providing the only build tool chains specifically designed to optimize software for the Cortex®-A9 and Cortex-A53 processors in Altera’s SoC portfolio.
• Debug support for ARM Cortex-A53 quad-core processor in Stratix® 10 SoC, including FPGA-Adaptive Debug capabilities for removing the debug barrier between the multi-core subsystem and FPGA fabric.

The companies also agreed to a long-term OEM agreement for DS-5 Altera Edition to provide support for all future ARM-based Altera SoC devices, ensuring a consistent, industry-leading software development platform across Altera’s portfolio of SoC FPGAs.
ARM DS-5 Altera Edition Yields Unprecedented Developer Productivity ARM Development Studio 5 is ARM’s flagship tools solution for embedded software development. ARM DS-5 Altera Edition is a complete tools solution exclusively for Altera SoCs, sold and distributed by Altera, and optimized to remove the debugging barrier between the integrated multi-core CPU subsystem and the FPGA fabric. The new DS-5 Altera Edition provides a substantial productivity gain for product development based on Altera SoC FPGAs. Key features include the following:

• Debug and trace support for 32-bit dual-core Cortex-A9 CPUs in Cyclone® V, Arria® V and Arria 10 SoCs and 64-bit quad-core Cortex-A53 in Stratix 10 SoCs
• ARM Compiler 5 (ARMv7) and ARM Compiler 6 (ARMv8) tool chains
• FPGA-Adaptive Debug support for SoC FPGAs, including software register views of IP programmed into the FPGA and cross-triggering between CPU and FPGA logic domains for hardware/software co-debugging
• Advanced trace, including time-correlated events in FPGA fabric with software events and processor instruction trace
• DS-5 Streamline™ performance analyzer for identification and correction of system-level bottlenecks


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