Microsemi Corporation, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the company’s new Mi-V™ ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilizing RISC-V open instruction set architectures (ISAs).
RISC-V, an ISA which is a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including portability as well as enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Microsemi’s new Mi-V ecosystem brings together a number of industry leaders involved in the development of RISC-V to leverage their capabilities and streamline RISC-V designs for customers.
Microsemi’s Mi-V ecosystem, part of Microsemi’s Accelerate Ecosystem, contains a number of components. Design tools include Microsemi’s SoftConsole Eclipse-based integrated development environment (IDE), the firmware catalog and Libero PolarFire system-on-chip (SoC). Operating systems include Express Logic’s ThreadX, Huawei LiteOS and Micrium µC/OS-II. Boards include the RTG4™ development kit, IGLOO™2 RISC-V board from Future Electronics, PolarFire Evaluation Kit and more. Debug dongles from Microsemi and Olimex, first-stage bootloaders and numerous soft peripherals are also included. Example projects, drivers and firmware are all available on GitHub, the world’s largest repository of open source software. Deployment of soft CPUs implemented with the R11C-V ISA is automatic and delivered to the user’s desktop via Microsemi’s IP Catalog. No end user license agreements are needed to gain access to the soft CPUs. Using RISC-V soft CPUs within the Mi-V ecosystem is simple, easy and free.
Offering low power and an open architecture, Microsemi’s PolarFire™, RTG4™, SmartFusion™2 and IGLOO™2 field programmable gate array (FPGA)-based RISC-V soft CPU cores are ideal for developing a wide variety of applications within the aerospace and defense, industrial and security markets. The Mi-V soft CPU cores make them particularly suitable for applications including guided munitions, IoT, secure communications and wireline bridging.
Through Microsemi’s early involvement in the creation of the RISC-V Foundation, the company has an established leadership role in the emerging standard and ecosystem and is working closely with the nonprofit to ensure the ISA becomes an industry standard for a wide variety of computing devices. Ted Speers, head of product architecture and planning for Microsemi’s Programmable business unit, was appointed to the inaugural board of directors of the RISC-V Foundation in July 2016, and Ted Marena, director of SoC FPGA marketing, was recently sworn in as chair of the RISC-V Marketing Committee after serving as vice-chair since August 2016. Marena will also be the featured speaker at EE World Online’s upcoming webinar titled, “The RISC-V ecosystem is ready for prime time. Get started here!” on Oct. 25, 2017. Attendees can register online to join this event.
The Mi-V Ecosystem began as part of the Microsemi Accelerate Ecosystem, a program designed to reduce time to market for end customers and time to revenue for ecosystem participants. Microsemi’s Accelerate Ecosystem brings together leading silicon, intellectual property (IP), systems, software and design experts to deliver solutions for end customers. Learn more at http://www.microsemi.com/design-support/accelerate-ecosystem-partners.
Microsemi Corporation | www.microsemi.com