Imperas Software Ltd., the leader in RISC-V processor verification solutions, announced that the Free riscvOVPsimPlus™ RISC-V reference model and simulator, which has been widely adopted across the RISC-V ecosystem, has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. Additionally, included in the updated model are the full standard CLIC features, Debug Module / Mode, Hypervisor “H” simulation, and also ‘near-ratified’ ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.
riscvOVPsimPlus is an Instruction Accurate RISC-V processor simulator (ISS) based on the Imperas Open Virtual Platform (OVP) technology with proprietary Just-in-Time Code Morphing simulation technology that executes RISC-V code on a Linux or Windows x86 based host computer. The riscvOVPsimPlus simulator is easy to understand and effective to use. It is flexible, accurate, and exceptionally fast, often over 2,000 MIPS on a modestly configured host machine. It is suitable as a platform target to develop bare‑metal, OS Ports (Linux or RTOS), driver development as well as full application software.
As a member of the RISC-V community of software, verification and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the free riscvOVPsimPlus simulator to assist RISC-V adopters to become compliant to the RISC-V specifications. The Imperas RISC-V reference models and simulation technology has been used within RISC-V International’s compliance test suite since 2018, and also in verification working groups within CHIPS Alliance and the OpenHW Group.
“Software and hardware co-design is essential for modern domain specific devices in applications such as AI and Machine Learning,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the new riscvOVPsimPlus offering, we are enabling adopters to explore the full envelope of the RISC-V Specifications with support for both for early software development and hardware verification. The RISC-V ISA Specification defines the hardware-software boundary and designers can start innovating now by adopting the free Imperas riscvOVPsimPlus.”
riscvOVPsimPlus is configurable to represent exactly the same implementation choices that RISC-V processor implementors choose thus making it an excellent tool for the usage of RISC-V application software and verification and architectural validation / compliance test suites.
The simulator can connect to GDB and Eclipse for source code debug and can be run in batch mode for regression testing and use in continuous integration environments. It also has many trace options to assist in program development. riscvOVPsimPlus has built-in instruction functional coverage measurement and reporting to assess both test quality and progress in test plan metrics. It is used to measure the completeness of the RISC-V architectural tests and test suites.
RISC-V Specifications and Versions currently supported in riscvOVPsimPlus
• RISC-V – Instruction Set Manual, Volume I: User-Level ISA
– Version 2.2 :
– Version 2.3 : Equivalent to 20190305
– Version 20190305 : Base-Ratification
• RISC-V – Instruction Set Manual, Volume II: Privileged Architecture
– Version 1.10 :
– Version 1.11 : Equivalent to 20190405
– Version 20190405 : Priv-MSU-Ratification
– Version master : Master Branch (1.12 draft)
• RISC-V “V” – Vector Extension (vector version)
– Version 0.7.1 : draft-20190605 :
– Version 0.8 : draft-20190906 :
– Version 0.8 : draft-20191004 :
– Version 0.8 : draft-20191117 :
– Version 0.8 : draft-20191118 :
– Version 0.8 :
– Version 0.9 :
– Version master : Master Branch as of commit 511d0b8
• RISC-V “B” – Bit Manipulation Extension
– Version 0.90 : draft-20190610
– Version 0.91 : draft-20190829
– Version 0.92 : draft-20191108
– Version 0.93 : draft-20200129
– Version master : Master Branch as of commit c1bd8ee
• RISC-V “K” – Cryptographic Extension (Scalar)
– Version 0.7.2: draft
• RISC-V “H” – Hypervisor Extension
– Version 0.6.1: draft
• RISC-V Debug Module
– Version 0.13.2: draft
– Version 0.14.0: draft
• RISC-V “I” – Base ISA
• RISC-V “E” – Embedded ISA
• RISC-V “M” – Multiply/Divide
• RISC-V “A” – Atomic Instructions
• RISC-V “F” – Single precision floating point
• RISC-V “D” – Double precision floating point
• RISC-V “C” – Compressed instructions
• RISC-V “S” – Supervisor mode
• RISC-V “U” – User mode
• RISC-V “N” – User-level interrupts
riscvOVPsimPlus, is a free RISC-V reference model and simulator that includes a proprietary freeware license from Imperas, which covers free commercial as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license, and is available for download now at www.ovpworld.org/riscvOVPsimPlus
Imperas commercial products
Imperas full commercial products provide full hardware design verification solutions including golden reference models, simulators, advanced analysis and debug tools that support custom RISC-V extensions and virtual platforms to model complete multi-core heterogeneous SoC and system level designs.