Synopsys, Inc. announced advancements across its leading hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support the ever-expanding demand for AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company’s unique software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying the world’s most sophisticated multi-die and AI chips amidst compounding design complexity and time-to-market requirements.
AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Simultaneously, edge AI architectures are driving aggressive throughput, latency, and power-efficiency targets that further expand the design and validation workload. To keep pace, the industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles, enabling first-time-right silicon and a seamless ability to integrate heterogeneous AI systems.
Comments
“As AI becomes more pervasive across almost every industry and products are now workload-optimized and silicon-powered, building high confidence early that the workloads are running to spec on the silicon under development is critical,” said Ravi Subramanian, Chief Product Management Officer at Synopsys. “Our software-defined, hardware-assisted verification solutions deliver continuous innovation. They are a powerful force multiplier to scale verification productivity and meet the growing demand for pre-silicon development across industries.”
“As NVIDIA’s AI platforms have become software-defined to meet rising performance and scalability demands, verification must evolve in the same way,” said Narendra Konda, Vice President, Hardware Engineering at NVIDIA. “Synopsys’ software-defined hardware-assisted verification and the new HAPS-200 12 FPGA systems are accelerating our system-level verification and validation, helping us deliver complex AI platforms on aggressive schedules. And, Synopsys modular hardware-assisted verification enables deeper collaboration across our ecosystem.”
The latest advancements across Synopsys’ software-defined hardware-assisted verification portfolio include:
Breakthrough performance and capacity for the AI era
The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, the industry’s highest capacity-scalable emulation platform, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. Modular HAV for HAPS enables the largest prototypes for software development, with further improvements for compute, storage, and bring-up capabilities.
New HAPS and ZeBu platforms
The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity and high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. They deliver 2x higher capacity compared to previous 6 FPGA platforms utilizing the latest AMD Versal™ adaptive SoCs, offering EP-Ready Hardware-enabled configurability between prototyping and emulation. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits.
Software-defined HAV capabilities extend system lifetime value
Continuous software improvements deliver compounding performance gains, increased debug productivity, as well as additional use case capabilities for both new and installed systems. The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. For safety-critical and high-reliability designs, new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping.
Availability & Additional Resources
Software-defined enhancements are being rolled out continuously across the HAV portfolio, with the new capabilities available to users today. The new EP-Ready HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms are available today and in Q3 2026, respectively. HAPS-200 1 FPGA platform is available today.