SEGGER adds 64-bit RISC-V support to Embedded Studio
SEGGER’s new release of Embedded Studio for RISC-V adds support for 64-bit RISC-V CPUs, including…
SEGGER’s new release of Embedded Studio for RISC-V adds support for 64-bit RISC-V CPUs, including…
With a combined 100 years of experience and 10 years of effort creates new ImperasDV killer-app for RISC-V verification engineers
As the Linux open-source operating system marks its 30th anniversary, Analog Devices, Inc. (ADI) announces…
Analog Devices, Inc. (ADI) introduced today the ADI EagleEye™ ADSW4000 PeopleCount algorithm for people detection…
Outlines vision for best-in-class RISC-V quality
The latest version of the Universal Debug Engine® (UDE) from PLS Programmierbare Logik & Systeme…
4Q2021 release of Imperas simulator and reference models supports latest RISC-V Extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0 plus Privilege Specification 1.12 as RISC-V Board formal approval is completed
Optimizing automotive software based on EB tresos AutoCore OS, ETAS RTA-OS, and Vector MICROSAR
Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) enhances the PSoC™ 6 family of microcontrollers (MCUs) with…
SEGGER, working with TÜV Rheinland, has neutralized its carbon footprint for 2020 and plans to continue to do so in the future.