Imperas

These latest models support the NS family of standard processors in safety-critical and next-generation embedded systems, for developers using Imperas and other leading EDA tools

ImperasDV is based on the trusted Imperas reference models and Verification IP, combined with architectural validation test suites and coverage libraries, and with native RVVI support

Imperas reference model for IMG RTXM-2200 is available on request to lead customers for real-time embedded applications in next generation domain-specific SoCs

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites

Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals

New open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification