Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the development of processor technologies for automotive systems-on-chip (SoCs) used in applications such as advanced driver assistance systems (ADAS) and autonomous driving (AD) systems that aim to optimize both performance and power efficiency while supporting a high level of functional safety. Renesas’ successful development announced today includes: 1) A convolutional neural network (CNN) hardware accelerator core that delivers a world-class combination of deep learning performance of 60.4 trillion operations per second (TOPS) and a power efficiency of 13.8 TOPS/W; 2) sophisticated safety mechanisms for fast detection of and response to random hardware failures. This makes it possible to create a highly power efficient detection mechanism with a high failure detection rate; 3) A mechanism that allows software tasks with different safety levels to operate in parallel on the SoC without interfering with each other, thereby bolstering functional safety for ASIL D control. These technologies have been applied in the company’s latest R-Car V3U automotive SoC.
Renesas presented these achievements at the International Solid-State Circuits Conference 2021 (ISSCC 2021), which took place February 13 to 22, 2021.
Applications such as next-generation ADAS and AD systems require outstanding deep learning performance of 60 TOPS or even 120 TOPS alongside power efficiency. In addition, since signal processing from object identification to the issuing of control instructions constitutes the bulk of the processing load in AD systems, achieving the functional safety equivalent to ASIL D – the strictest safety level defined in the ISO 26262 automotive safety standard – is a pressing issue. Renesas has developed new technologies to meet these needs, including a hardware accelerator that delivers outstanding CNN processing performance with superior power efficiency.
The newly-developed technologies used in the R-Car V3U SoC are described below.
1 Development of high-performance CNN hardware accelerator with superior power efficiency
As the number of sensors utilized in next-generation ADAS and AD systems increases, more powerful CNN processing performance is required. In addition, there is a need to reduce the heat generated by power consumption to make possible electronics control units (ECUs) that are air-cooled, which brings advantages in weight and cost. Renesas has developed a CNN hardware accelerator core with superior deep learning performance and implemented three such cores, in a high-density configuration, on the R-Car V3U. In addition, the R-Car V3U has 2 megabytes (MB) of dedicated memory per CNN accelerator core, for a total of 6 MB of memory. This reduces data transfers between external DRAM and the CNN accelerator by more than 90 percent and successfully achieved a high CNN processing performance of 60.4 TOPS with best-in-class power efficiency of 13.8 TOPS/W (Note 1).
2 Development of safety mechanisms for ASIL D systems capable of self-diagnosis
The ISO 26262 automotive functional safety standard specifies numerical targets (metrics) for various functional safety levels. The metrics for ASIL D, the highest functional safety level, are 99 percent or above for the single point fault metric (SPFM) and 90 percent or above for the latent fault metric (LFM), which means that an extremely high detection rate is required for random hardware failures. In addition, due to the higher level of involvement in vehicle operation of systems such as next-generation ADAS and AD systems, automotive SoCs overall have come to incorporate more functions subject to ASIL D requirements. Renesas has developed safety mechanisms for fast detection of and response to random hardware failures occurring in the SoC overall. Both reduced power consumption and a high failure detection rate are achieved by combining safety mechanisms suited to specific target functions. The incorporation of these mechanisms into the R-Car V3U is expected to bring the majority of the SoC’s signal processing into achieving the ASIL D metrics. An SoC that satisfies the ASIL D metrics is capable of independent self-diagnosis, and this reduces the complexity of fault tolerant design in an AD system.
3 Development of a support mechanism for freedom from interference (FFI) between software tasks
Achieving freedom from interference (FFI) between software tasks is an important aspect of meeting functional safety standards. When software components with different safety levels are present in the system, it is essential to prevent lower-level tasks from causing dependent failures in higher-level tasks. In addition, an issue of particular importance in SoCs is ensuring FFI when accessing control registers in various hardware modules and shared memory. Renesas has developed an FFI support mechanism that monitors all data flowing through interconnects in the SoC and blocks unauthorized access between tasks. This enables FFI between all tasks operating on the SoC, making it possible to realize an SoC for ASIL D applications capable of managing object identification, sensor fusion with radar or LiDAR, route planning, and issuing of control instructions with a single chip.
Note 1) The performance of the CNN hardware accelerator was measured on an optimized network.