Reference Design Implemented Using Renesas LLDRAM-III and FPGA Technology, Supporting Traffic in the 100-Gigabit Class.
Renesas Electronics, a premier supplier of advanced semiconductor solutions, announced a packet header search reference design for 100 Gigabit (Gb) communications devices such as routers, switches, and servers.
The Renesas reference design is comprised of the LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA device, and development support tools. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60 percent.
With the arrival of the Internet of Things (IoT) era and the rapid increase in the volume of data flowing to and from connected devices, increasing network speeds has become a priority. In particular, more data centers are switching their traffic speeds from 40 Gb to 100 Gb to support the increasing volume of data, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Also, widespread adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. Against this background, Renesas has developed a power-efficient packet header search reference design able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries.
Key features of the packet header search reference design:
1) Packet header search of one million entries or more in 100Gb traffic using only two watts of power, equivalent to power consumption of 40Gb traffic
2) Flexible search key length functionality that eliminates the need for modifications to the search IP design to accommodate new communication protocols
3) Fully integrated reference design kit can shorten development time needed for designing network equipment by approximately six months
Renesas provides NSEs for the complex communication processing at the 200-Gb class used by external communication interfaces of data centers and backbone communication networks. For communication processing at 100 Gb and below, in applications within data centers having large numbers of ports, Renesas provides a packet header search reference design composed of LLDRAM-III and FPGA. With this new FPGA-based search solution that enables flexible communication and support for rapidly-advancing network technology, Renesas continues its commitment to the communications market with the development of new solutions.
Renesas Electronics Europe