Altera FPGA-Based Storage Reference Design Doubles Life of NAND Flash

18 JULY 2015

Altera Corporation has developed a storage reference design, based on its Arria® 10 SoCs, that doubles the life of NAND flash and can increase the number of

program-erase cycles by up to 7X compared to current NAND flash implementations. The reference design includes an Arria 10 SoC with an integrated dual-core ARM® Cortex®A9 processor, in an optimized, cost-effective, single-chip solution, leveraging a solid-state disk (SSD) controller from Mobiveil and NAND optimization software from NVMdurance. This reference design provides improved performance and flexibility in NAND utilization while reducing the cost of the NAND array by increasing the lifetime of data center equipment.
Using FPGAs with integrated hard processor systems, designers can quickly take advantage of the cost savings offered by next-generation NAND devices while retaining the flexibility to customize a solution that maximizes the performance, durability and storage capacity of their system. This storage solution implements Mobiveil’s Universal NVM Express Controller (UNEX), a configurable controller for PCIe-based SSDs, and NVMdurance’s NAND flash optimization software in an Arria 10 SoC, enabling data centers to leverage the most advanced 3D NAND technology without the long design cycles required with ASIC designs. In this reference design, Mobiveil’s controller supports multi-core architectures, enabling threads to run on each core with their own queue and interrupt without any locks required. NVMdurance’s NAND flash optimization software constantly monitors the condition of the NAND flash and automatically adjusts the control parameters in real time, greatly extending the flash system’s endurance.

Altera
www.altera.com

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