23 DECEMBER 2008

Silicon Laboratories Inc., a leader in high-performance, analog-intensive, mixed-signal ICs, introduced a new family of clock generators and buffers that provide the most frequency flexibility in the industry. Based on Silicon Labs’ breakthrough MultiSynth™ technology, the Si5338 is capable of synthesizing any frequency from 0.16 to 350 MHz and select frequencies to 700 MHz on each of the device’s four differential outputs, dramatically simplifying timing architectures by replacing four discrete phase-locked loop (PLL) devices with a single IC. Consistent with Silicon Labs’ timing strategy of providing the most frequency flexible clock and oscillator solutions in the industry, the Si5338 provides best-in-class performance and integration while shortening design cycles for applications such as next generation communications equipment, wireless base stations, broadcast video, test and measurement and data acquisition. At one picosecond rms random jitter typical, the Si5338 is able to simultaneously generate low jitter clocks for a wide variety of ICs, including processors, FPGAs, ASICs, memory and physical layer transceivers. The device generates four differential or eight single-ended outputs per device, eliminating the need for external clock distribution buffers. In addition to frequency, each output clock is independently configurable in terms of supply voltage (1.5V, 1.8V, 2.5V, 3.3V) and signal format (LVPECL, LVDS, CMOS, HCSL, SSTL, HSTL), eliminating the need for external level translators and thereby reducing BOM cost and complexity.
Historically, complex timing architectures have required multiple clock generators and/or standalone crystal oscillators (XOs) to provide the range of frequencies needed by the end application, often at the expense of cost, design complexity and power. The any-rate, any-output capability provided by the Si5338 dramatically simplifies timing architectures by replacing fixed frequency clock generators, discrete level translators and crystal oscillators with a single device, minimizing cost and real estate and reducing power by 50 percent compared to traditional solutions. To simplify board-level test, the Si5338 includes a frequency margining feature that enables the frequency of each output clock to be varied dynamically over the 0.16 to 350 MHz range, eliminating discrete XOs and making it easier for hardware designers to guarantee consistent, reliable system operation over temperature and voltage.
For applications that do not require the programmability provided by the Si5338, Silicon Labs is also introducing a broad portfolio of Si5334 pin-controlled clock generators. More than 70 Si5334 devices are available for popular Ethernet, Fibre Channel, PCI Express, T1/E1, broadcast video (HDTV) and SONET/SDH OC-3/12/48 applications.

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